The present invention relates to a method for testing a semiconductor memory device, and in particular, a method for performing a multi-bit parallel test with a comparatively small area, without affecting a normal operation of the semiconductor memory device.
High-integration of semiconductor memory devices generally tends to increase their production cost due to increase of their chip area. In particular, the higher the integration in semiconductor memory devices becomes, the more time and cost for testing the same is required.
Therefore, a known method has been recently used to save the time and cost of testing, in which instead of serial data access, multiple bits are simultaneously tested in parallel. FIG. 1 shows a construction of a known memory device for such a parallel test, wherein 8-bit parallel data are processed for testing.
Referring to FIG. 1, each one of four pairs of data bus DB.sub.0-3 is coupled to each output of eight data sensing/driving circuits 3 to 10 receiving each pair of data through each pair of input/output lines IO.sub.0-7 from either one of two memory cell groups 1 and 2 Four transmission gates 11 to 14 are located at the center of the data bus pairs, for disconnecting or connecting the data bus pairs each coupled to a left group of the data sensing/driving circuits 3 to 6 and a right group of the data sensing/driving circuits 7 to 10. These transmission gates 11 to 14 are constructed with N-channel and P-channel MOS transistors having each gate coupled to receive either directly or through inverter 15, a parallel test enable signal .phi..sub.PTE. To other end of the data bus pairs is coupled a data selection circuit 16 to which a data output buffer (not shown) is further connected. A pair of first comparators 17 and 19 have inputs coupled with each pair of the data bus and have each output to deliver a pair of data to a second comparator 18. A switching circuit 20 is connected between the second comparator 18 and the data output buffer and the data selection circuit 16. The first comparators 17 and 19, the data selection circuit 16, the second comparator 18 and the switching circuit 20 are in common controlled by the parallel test enable signal .phi..sub.PTE, as in the transmission gates 11 to 14. According to this construction of 8-bit parallel test method, once eight pairs of data are provided through eight pairs of the input/output line from the two memory cell groups 1 and 2, the data are sensed and amplified and then driven by the data sensing and driving circuits 3 to 10, prior to transmission to the four data bus pairs, respectively. The eight pairs of transmitted data are, each in four pairs, provided to both first comparators 17 and 19 which respectively decode the received data into each pair of data to the second comparator 18. Then the second comparator turns the received two data pairs into a single pair of data, which data are delivered to the data output buffer through the switching circuit 20.
At this stage, as the parallel test enable signal .phi..sub.PTE is a logic high state designating a test mode, the transmission gates 11 to 14 coupling the right and left data bus pairs together upon a normal mode are all turned off, and the data selection circuit 16 also does not function. On the contrary, in a normal mode, as the signal .phi..sub.PTE is a logic low state, the first and second comparators 17, 19 and 18, and the switching circuit 20 do not function. Therefore, in a normal mode, there is provided a data transmission path in a sequence of the memory cell groups 1 and 2--the data sensing and driving circuits 3 to 10--the data bus pairs--the data selection circuit 16--the data output buffer, and wherein the transmission gates 11 to 14 are, of course, turned on, whereas in a test mode, there is provided another data transmission path in sequence of the memory cell groups--the data sensing/driving circuit the data bus pairs--the first comparators 17 and 19--the second comparator 18--the switching circuit 20--the data output buffer, and wherein the transmission gates are turned off.
However, with the above described prior art construction, there arises a drawback of low operation speed, since the data selected from the left memory cell group must always pass through the transmission gates 11 to 14 to be transmitted to the data output buffer, during a normal mode. Moreover, in the prior art test method, since the data must be passed through a driver, which is located inside the data sensing/driving circuit 3 to 10, during a normal mode, the power consumption therein inevitably increases. In addition, existence of the transmission gates leads to an undesirable increase of the entire chip area in a high-integration memory device with a large number of data bus pairs.